Research
Research
Cryptography Department - Publications
[52] - C. D. Walter, Simple Power Analysis of Unified Code for ECC Double and Add, Cryptographic Hardware and Embedded Systems - CHES 2004, J.-J. Quisquater & M. Joye (editors), Lecture Notes in Computer Science, Springer-Verlag, 3156, pp 191-204. Abstract, Notes.
[51] - C. D. Walter, Issues of Security with the Oswald-Aigner Exponentiation Algorithm, Topics in Cryptology - CT-RSA 2004, Tatsuaki Okamoto (editor), Lecture Notes in Computer Science, Springer-Verlag, 2964, pp 208-221. Abstract, Powerpoint Slides & Notes.
[50] - M. Arnold, T. Bailey, J. Cowles & C. Walter, Fast Fourier Transforms using the Complex Logarithm Number System, J. VLSI Signal Proc., vol 33, pp. 325-335, 2003.
[49] - W. Schindler & C. D. Walter, More Detail for a Combined Timing and Power Attack against Implementations of RSA , Proceedings of the Ninth IMA International Conference on Cryptography and Coding, K. Paterson (editor), Lecture Notes in Computer Science, Springer-Verlag, 2898, pp 245-263. Abstract, Powerpoint Slides & Notes.
[48] - C. D. Walter, Longer Keys may facilitate Side Channel Attacks, Proceedings of the Tenth Annual Workshop on Selected Areas in Cryptography - SAC 2003, 14-15 Aug 2003, Carleton University, Ottawa. M. Matsui & R. Zuccherato (editors), Lecture Notes in Computer Science, Springer-Verlag, 3006, pp 42-57. Powerpoint Slides & Notes.
[47] - C. D. Walter, Ç. Koç & C. Paar (editors), Cryptographic Hardware and Embedded Systems - CHES 2003, Lecture Notes in Computer Science, vol. 2779, Springer-Verlag, 2003, 441 pp.
[46] - C. D. Walter, Security Constraints on the Oswald-Aigner Exponentiation Algorithm, Cryptology ePrint Archive: Report 2003/013, IACR, 22 Jan 2003.
[45] - C. D. Walter, Seeing through Mist Given a Small Fraction of an RSA Private Key, Topics in Cryptology - CT-RSA 2003, Marc Joye (editor), Lecture Notes in Computer Science, vol. 2612, Springer-Verlag, 2003, pp. 391-402. Abstract, Powerpoint Slides & Notes.
[44] - C. D. Walter, Breaking
the Liardet-Smart Randomized Exponentiation Algorithm
Proc.
CARDIS
'02, San Jose, 21-22 Nov 2002, USENIX Assoc, 2002, pp 59-68.
Powerpoint Slides.
[43] - C. D. Walter, Some Security Aspects of the MIST Randomized Exponentiation Algorithm, Cryptographic Hardware and Embedded Systems - CHES 2002, B. S. Kaliski, Ç. Koç & C. Paar (editors), Lecture Notes in Computer Science, vol. 2523, Springer-Verlag, 2002, pp. 276-290. Abstract, Powerpoint Slides & Notes,
[42] - C. D. Walter and D. Samyde, Data Dependent Power Use in Multipliers, Proc. 17th IEEE Symposium on Computer Arithmetic (ARITH-17), Cape Cod, 27-29 June, 2005, IEEE Press, 2005, pp. 4-12.
[41] - C. D. Walter, MIST: An Efficient, Randomized Exponentiation Algorithm for Resisting Power Analysis, Topics in Cryptology - CT-RSA 2002, B. Preneel (ed.), Springer LNCS vol. 2271, pp 53-66. Powerpoint Slides & Notes from the presentation at RSA 2002 Cryptographers' Track, San Jose, CA, February 18-22, 2002.
[40] - C. D. Walter, Precise Bounds for Montgomery Modular Multiplication and Some Potentially Insecure RSA Moduli, Topics in Cryptology - CT-RSA 2002, B. Preneel (ed.), Springer LNCS vol. 2271, pp 30-39. Powerpoint Slides & Notes from RSA 2002 Cryptographers' Track, San Jose, CA, February 18-22, 2002.
[39] - C. D. Walter, Improvements in, and relating to, Cryptographic Methods and Apparatus , UK Patent Application 0126317.7 (only draft available). This is described above in [41] & [43] and is owned by Comodo Research Lab Ltd.
[38] - M. G. Arnold & C. D. Walter, Unrestricted Faithful Rounding is Good Enough for some LNS Applications, Proc. 15th IEEE Symposium on Computer Arithmetic (ARITH 15), Vail, Colorado, 11-13 June, 2001, IEEE Press, 2001, pp 237-246. Powerpoint Slides & Notes.
[37] - C. D. Walter, Is there Safety in Numbers against Side Channel Leakage?, RSA Europe Conference (crypto track), Amsterdam, 15-18th October, 2001. Powerpoint Slides & Notes.
[36] - C. D. Walter, Sliding Windows Succumbs to Big Mac Attack, Cryptographic Hardware and Embedded Systems - CHES 2001, Ç. Koç, D. Naccache & C. Paar (editors), Lecture Notes in Computer Science, vol. 2162, Springer-Verlag, 2001, pp. 286-299. Powerpoint Slides & Notes.
[35] - C. D. Walter & S. Thompson, Distinguishing Exponent Digits by Observing Modular Subtractions, Topics in Cryptology - CT-RSA 2001, D. Naccache (editor), Lecture Notes in Computer Science, vol. 2020, Springer-Verlag, 2001, pp. 192-207. (This is work supported by Datacard Consult P7.) Powerpoint slides from RSA 2001, Cryptographers' Track, San Francisco, 8-12 April, 2001.
[34] - C. D. Walter, Improved Linear Systolic Array for Fast Modular Exponentiation, IEE Computers and Digital Techniques, vol. 147, no. 5, September 2000, pp. 323-328.
[33] - C. D. Walter, Data Integrity in Hardware for Modular Arithmetic, Proc. Cryptographic Hardware and Embedded Systems (CHES 2000), Worcester, MA, Aug 17-18, 2000, Christof Paar & Çetin Koç, editors, Springer Lecture Notes in Computer Science, vol. 1965, pp. 204-215. Powerpoint slides.
[32] - C. D. Walter, Montgomery Exponentiation Needs No Final Subtractions, Electronics Letters, vol. 35 no. 21, October 1999, pp 1831-1832.
[31] - C. D. Walter, An Overview of Montgomery's Multiplication Technique: How to make it Smaller and Faster, (invited talk) Proc. Workshop on Cryptographic Hardware and Embedded Systems, (CHES 99), Worcester, MA, Aug 12-13, 1999, Christof Paar & Çetin Koç, editors, Springer Lecture Notes in Computer Science, vol. 1717, pp 80-93. Powerpoint slides.
[30] - C. D. Walter, Moduli for Testing Implementations of the RSA Cryptosystem , Proc. 14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, 14-16 April, 1999, IEEE Press, 1999, pp 78-85.
[29] - N. Nedjah, C. D. Walter & S. E. Eldridge, Efficient Automata-Driven Pattern Matching for Equational Programs, Software Practice & Experience, vol. 29, no. 9, 1999, pp. 793-813.
[28] - C. D. Walter, Techniques for the Hardware Implementation of Modular Multiplication, Proc. 2nd IMACS Internat. Conf. on Circuits, Systems & Computers, Athens, Oct 1998, vol. 2, pp 945-949.
[27] - C. D. Walter, Exponentiation using Division Chains, IEEE Transactions on Computers, vol. 47, No. 7, July 1998, pp. 757-765. (This is an extended and improved version of what was presented at Arith 13, Asilomar, Proceedings, IEEE Press, 1997, pp. 92-98.)
[26] - C. D. Walter, Analysis of Delays in Converting from a Redundant Representation, IEE Computers & Digital Techniques, 144 No 4, (July 1997), pp. 219-221.
[25] - C. D. Walter, Space-Time Trade-Offs for Higher Radix Modular Multiplication using Repeated Addition, IEEE Transactions on Computers, 46 (1997), No. 2, pp. 139-141.
[24] - N. Nedjah, C. D. Walter & S. E. Eldridge, More efficient Pattern-Matching Automata for Overlapping Patterns, Proc. International Workshop on the Implementation of Functional Languages, St Andrews, Sept 1997, pp 341-350.
[23] - N. Nedjah, C. D. Walter & S. E. Eldridge, Optimal Left-to-Right Pattern-Matching Automata for Equational Programs, Proc. of ALP97 & HOA97, Lecture Notes in Computer Science, vol. 1298, 1997, pp. 273-286.
[22] - C. D. Walter, Verification of Hardware combining Multiplication, Division & Square Root, Microprocessors & Microsystems 19 (1995), pp. 243-245.
[21] - C. D. Walter, Still Faster Modular Multiplication, Electronics Letters 31 (1995) No 4, pp. 263-264.
[20] - C. D. Walter, Optimal Parameters for Fully On-Line Arithmetic, International J. of Computer Mathematics 56 (1995), pp.11-18.
[19] - C. D. Walter, Improving Average Delay for On-Line Algorithms, Electronics Letters 30 (1994), No. 23, pp. 1925-6.
[18] - C. D. Walter, Logarithmic Speed Modular Multiplication, Electronics Letters 30 (1994), No 17, pp. 1397-8.
[17] - C. D. Walter, Systolic Modular Multiplication, IEEE Transactions on Computers 42 (1993), pp. 376-378.
[16] - S. E. Eldridge & C. D. Walter, Hardware Implementation of Montgomery's Modular Multiplication Algorithm, IEEE Transactions on Computers 42 (1993), pp. 693-9.
[15] - C. D. Walter, Faster Modular Multiplication by Operand Scaling, Proc. CRYPTO '91, Lecture Notes in Computer Science 576 (1992), pp. 313-323, Springer-Verlag.
[14] - C. D. Walter, Fast Modular Multiplication using 2-Power Radix, International J. of Computer Mathematics, 3 (1991), pp. 21-28.
[13] - C. D. Walter & S. E. Eldridge, Specification and Verification of Software, Concise Encyclopedia of Software Engineering, D. Morris & B. Tamm editors, Pergamon Press, 1991, pp. 331-338.
[12] - C. D. Walter, Formal Methods, Concise Encyclopedia of Software Engineering, D. Morris & B. Tamm editors, Pergamon Press, 1991, pp. 135-138.
[11] - C. D. Walter & S. E. Eldridge, A Verification of Brickell's Fast Modular Multiplication Algorithm, International J. of Computer Mathematics 33 (1990), pp. 153-169.
[10] - (Book) R. Dowsing, V. J. Rayward-Smith & C. D. Walter, A First Course in Formal Logic and its Applications in Computer Science, Blackwell Scientific Publications, Oxford, 1986 (265pp + vi).
[9] - C. D. Walter, UMIST OBJ Manual, version 1.0, Technical Report, Computation Department, UMIST, 1986, 28+iii pp.
[8] C. D. Walter, Adjacency Matrices, SIAM J. Algebraic & Discrete Methods, 7 (1986) pp. 18-29.
[7] C. D. Walter, Intersection numbers for coherent configurations and the spectrum of a graph, J. of Combinatorial Theory (B) 35(1983), pp. 201-204.
[6] C. D. Walter, Pure fields of degree 9 with class number prime to 3, Annales de l'Institut Fourier, Grenoble 30 (1980), pp. 1-16.
[5] C. D. Walter, The ambiguous class group and the genus group of certain non-normal extensions, Mathematika 26 (1979), pp. 113-124.
[4] C. D. Walter, Kuroda's class number relation, Acta Arithmetica 35 (1979), pp. 41-51.
[3] C. D. Walter, Brauer's class number relation, Acta Arithmetica 35 (1979), pp. 33-40.
[2] C. D. Walter, A class number relation in Frobenius extensions of number fields, Mathematika 24 (1977), pp. 216-225.
[1] C. D. Walter & C. J. Parry, The class number of pure fields of prime degree, Mathematika 23 (1976), pp. 220-226.
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